DUE DATE: 24th April 2017, 12PM
 Your assignment solutions are to be submitted at the assignment box at the school office.
 Attach completed and signed assignment submission form as a front page to your submission.
 For each of the design question, you may use Xilinx ISE or any other appropriate CAD tool to simulate and verify your design.
 Attach all design and simulation materials such as schematic diagram (or HDL), simulation output and testing fixture.
Question 1
An Arithmetic Logic Unit (ALU) is at the heart of all computers as well as most digital hardware systems. It is a combinational network that performs logical and arithmetic operations. An n-bit ALU typically has two input words A and B, each of which denoted by A=An-1An-2…Ao and B = Bn-1Bn-2…Bo. The output word is denoted by F = Fn Fn-1…Fo, where the high order output Fn is actually a carry-out. In addition, there is a carry-in input Co. Besides data inputs and outputs, an ALU must have control inputs for specifying the operations to be performed. The control inputs include a mode selector, M, and operation selector inputs, So and S1. The mode selector is needed to decide whether logical or arithmetic operation is to be performed and the operation select inputs are required to determine which particular logic or arithmetic function is to be performed. The specification of a simple ALU bit slice, that is the behaviour of a single bit of an ALU, is given in Table 1. The operations are broken down into three sections: logical operations, arithmetic operations where the carry-in is 0, and arithmetic operations where the carry-in is 1.
Based on the specification, design an 8-bit ALU. Your design should begin with a 1-bit slice of the ALU and then cascade them to build the desired 8-bit ALU. Note the single bit slice will have six inputs: Ai, Bi, Ci, M, S1, and So, and two outputs: Fi and Ci+1 (carry-out). Your design should include your choice of circuit implementation, simulation and verification. For the purpose of this assignment, it will be suffice to show the simulation and verification of the 1-bit slice of the ALU. Your design should aim at achieving optimized implementation and include calculation of gate input cost.
M=0, Co=X
S1 So
0 0
0 1
1 0
1 1
Logical Bitwise Operation
Fi = Ai
Fi = NOT Ai
Fi = Ai XOR Bi
Fi = Ai XNOR Bi
M=1, Co=0
S1 So
0 0
0 1
1 0
1 1
Arithmetic Operations
F = A
F = A + B
F = (NOT A) + B
M=1, Co=1
S1 So
0 0
0 1
1 0
1 1
Arithmetic Operations
F = A + 1
F = (NOT A) + 1
F = A + B + 1
F = (NOT A) + B + 1
B – A
Table 1: Specification for ALU
Question 2
You are to design a combinational circuit block as part of a larger system that makes change from quarters (25 cents coin). There is a large reservoir of dimes (10 cents coin) and another one of nickels (5 cents coin). Two binary counters keep track of the number of dimes and nickels in each. The circuit block should work as follows:
It takes the low-order of bits of the dimes counter and the nickels counter and generates the number of dimes and nickels to give as change. In general, dimes should be given before nickels. For example, if there are at least two dimes left, these should be given with a single nickel, rather than five nickels. There is definitely a possibility that no change can be given before the reservoirs are (almost) exhausted of coins and “a no change available” sign should be illuminated. You do not need to design the binary counters for the dimes and nickels. But you will need them as inputs.
Although the vector length of the binary counters is not critical, for the purpose of this design you may assume the vector length of the binary counters as four. Your design should include your design procedure, choice of implementation, simulation. The gate input cost must be calculated.

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